1. Field of the Inventive Concept
The present inventive concept relates to a method of manufacturing a semiconductor device using a stress memorization technique (SMT).
2. Description of the Related Art
The conductivity of a channel region of a metal oxide semiconductor (MOS) transistor may be increased to improve the performance of the MOS transistor. For example, the lattice structure of the channel region may altered to increase the charge-carrier mobility and hence, the conductivity of the channel region.
A stress memorization technique (STM) is one of the techniques that can be used to alter the lattice structure of the channel region. Specifically, an STM entails forming an amorphous region near a channel region in which the channel of the MOS transistor will form, and annealing the amorphous region while a stress inducing layer is located on the amorphous region. The amorphous region is thus recrystallized in a state in which stress is exerted thereon by the stress inducing layer. As a result, deformed crystals are formed. The deformed crystals maintain their deformed state even after the stress inducing layer is removed. Accordingly, the stress is considered to be memorized in the deformed crystals.
The deformed crystals act as a stressor on the channel region, affecting the lattice structure of the channel region, and thereby increasing the charge-carrier mobility.
Meanwhile, during the recrystallization process of SMT, the crystals tend to grow at different rates in various crystallographic directions because the amorphous region is recrystallized under the stress induced therein by the stress inducing layer. For example, in the recrystallization process, the crystal growth rate may be greater in a <001> crystallographic direction than in a <110> crystallographic direction. In this case, a point at which crystal growth pinches off can appear near a (111) facet, thus creating a stacking fault, i.e., a defective region. Halo boron segregation can occur at the defective region, causing problems such as a reduction in the desired threshold voltage and undesired amounts of off-leakage current.